R5900 Emotion Engine CPU core

Figure 3.2. Block diagram of the Playstation 2 - Emotion Engine Core

The main CPU in the Playstation 2 is one developed by Toshiba, exclusively for the console. It is a 128-bit MIPS ISA level III compliant processor. The Emotion Engine (EE) is the chip that manages most of the other processors in the system, performing the role of a traditional CPU.

Some of its more advanced features include:

Floating Point Unit (FPU)

Figure 3.3. Block diagram of the Playstation 2 - Floating Point Unit

The floating point unit included in the EE core is a high performance single-precision floating-point unit. The designers of the FPU decided to not make it IEEE compliant and save some silicon. All this means is that the floating point numbers generated do not comply -exactly- to the IEEE spec, but the numbers should be close enough for most programmers. The FPU contains one multiply-add unit and one floating point divide unit.

Cache and Scratchpad RAM (SPR)

Due to the requirement of low manufacturing cost, the EE contains a very limited on-chip cache. 8KB of data cache and 16KB of instruction cache are included on-chip. There is also another cache specified as the Scratchpad that is used as a low-latency working area.

DMA, DRAM and Memory Management Unit (MMU)

The memory management unit, RDRAM controller and DMA controller handle all memory access within the system. The Playstation 2 is rated at performing a peak theoretical bandwidth of 3.2 GBps.

The DMA controller is a 10 channel controller that can DMA data between main memory and an I/O device (such as the IPU) as well as memory and scratchpad RAM.

The MMU is capable of doing 32-bit physical/logical address space conversion and has a 48-entry TLB to speed lookups.

Interrupt controller and Timers

The PS2 provides an interrupt for every device in the system as well as a special interrupt for the DMA controller. Four 16-bit timers are provided for high precision, processor cycle-level timing.